1. Field of the Invention
The present invention relates to a semiconductor device, especially, a semiconductor memory device including a MOS transistor and a semiconductor memory device having a new structure.
2. Description of the Related Art
As semiconductor memory devices, there are nonvolatile semiconductor memory devices (EEPROM), dynamic semiconductor memory devices (DRAM) and the like. An EEPROM will be described below.
A NAND cell type EEPROM which allows high integration is known as one of EEPROMs. In the NAND cell EEPROM, sources and drains of a plurality of memory cells are connected in series with each other to be commonly used by the adjacent memory cells, and connected to a bit line as one unit.
A memory cell generally has a MOSFET structure in which a charge storage layer (floating gate) and a control gate are stacked. A memory cell array is integrated in a p-type well formed on a p-type or n-type substrate. The drain side of the NAND cell is connected to the bit line through a selection gate. The source side of the NAND cell is connected to a source line (reference potential wire) through a selection gate. The control gates of the memory cells are continuously disposed in the row direction to serve as a word line.
The operation of the NAND cell type EEPROM is as follows.
The data write operation is sequentially performed from a memory cell at a position farthest from the bit line. A high voltage V.sub.pp (=about 20 V) is applied to the control gate of the selected memory cell. An intermediate potential V.sub.PPM (=about 10 V) is applied to the control gates and the selection gates of the memory cells on the bit line side. A voltage of 0 V or the intermediate potential is applied to the bit line in accordance with data. When a voltage of 0 V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell to cause charge injection from the substrate side to the floating gate.
With the above operation, the threshold value of the selected memory cell is shifted in the positive direction. This state is defined as, e.g., "1". Application of the intermediate potential does not cause charge injection, so that the threshold value is kept unchanged at the negative value. This state is defined as "0".
The data erase operation is simultaneously performed for all the memory cells in the NAND cell. More specifically, all the control gates are set to 0 V, and a high voltage of 20 v is applied to the selection gates, the bit line, the source line, the p-type well and the n-type substrate on which the memory cell array is formed. With this operation, charges in the floating gates are released to the substrate side in all the memory cells, and the threshold value is shifted to the negative direction.
The data read operation is performed as follows. A power supply voltage V.sub.CC is applied to the bit line, and a voltage of 0 V is applied to the source line. The control gate of the selected memory cell is set to 0 V, and the potential of the control and selection gates of the remaining memory cells are set to the power supply potential (=5 V). It is detected whether or not a current flows in the selected memory cell, thereby performing the data read operation.
In the structure of the conventional NAND cell type EEPROM, all the memory cells constituting the NAND cell are connected with each other through a source-drain diffusion layer. For this reason, the diffusion layer inevitably extends under the gates, and the effective channel length is decreased. This poses a problem on size reduction of a memory cell. As the memory cell becomes finer, the coupling capacitance between the control gate and the floating gate is decreased, resulting in a decrease in coupling factor of the memory cells.
As described above, in the conventional NAND cell type EEPROM, the diffusion layer extends under the gates to cause a decrease in effective channel length or coupling factor of the memory cells.
The above problem, which is a decrease in effective channel length or coupling factor of the memory cells, is not limited to NAND cell type EEPROMs, and also applies to DRAMs, MOS transistor or the like.